Hello everyone, I am currently working on simulating a multi-loop selection in Logix Designer. While I have set up the simulation, I am facing difficulties in configuring the "cvprevious/setcvprevious" functions. I am seeking advice from anyone who has experience with this. The 'override' loop I am working with functions normally, but experiences a delay when overriding under upset conditions. I believe that the cvprevious/setcvprevious functions could help in keeping the non-selected loops CV equal to the selected loops CV. For more information, you can refer to this document from Rockwell: [link].
In reference to the previous PID Loop RSLogix 5000 thread, it appears that the simulation is malfunctioning. To resolve this issue, consider utilizing the 'assume data available' indicator for the CVPrevious inputs. You can access this option by right-clicking on it. For more assistance with this problem, please refer to the CLX PIDE Problem thread.
In response to a user's comment in another thread about PID Loop in RSLogix 5000, it seems that the simulation is still not functioning correctly despite enabling the 'assume data available" indicator for both CVPrevious inputs. This could be indicative of a configuration error. I will continue troubleshooting to determine the cause of the issue.Visit the CLX PIDE Problem forum for more insights.
It seems like you're on the right track with the cvprevious/setcvprevious functions in handling the 'override' loop issue. These functions indeed work well in maintaining the equality between the CVs of the non-selected and selected loops. But also, in regards to the delay issue, consider checking your other control blocks. Make sure the dead time or the delay time parameter isn't set too high. This can also contribute to the upset condition situation. However, if the delay is inherent to the process itself, you might need to design a predictive control strategy. But as is common with Logix Designer, the devil is often in the detail. A careful line-by-line scan might reveal more.
Hey there, it seems like you're pretty deep into your Logix Designer project. I've been in a similar situation before where I needed to align the control variable (CV) in multiple loops. The cvprevious/setcvprevious functions are indeed useful for this. Remember that the setcvprevious function is typically used after you've made a change to the CV in the current loop; it essentially stores the current CV value for the next scan. To ensure there's no delay in the override loop during upset conditions, you might want to check your scan times and see if optimizing them can help mitigate the lagging issue. Also, don't forget to run a validation of your tag data, this may help identify if there are any issues with the current CV setup.
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Answer: - The "cvprevious/setcvprevious" functions in Logix Designer are used to help keep the non-selected loops' control variables (CV) equal to the selected loop's CV during simulation.
Answer: - One approach to troubleshooting delays in the "override" loop when overriding under upset conditions is to explore the use of the cvprevious/setcvprevious functions to maintain consistency in control variables.
Answer: - Yes, for more detailed information on multi-loop selection simulation in Logix Designer, you can refer to the document from Rockwell shared in the discussion thread.
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